A memory cell array of, for example, a read-only memory (ROM), typically includes a plurality of memory cells arranged in rows and columns. Word lines typically extend along and are connected to the rows of the memory cells, while bit lines extend along and are connected to the columns of the memory cells. Typically, each memory cell comprises a transistor, e.g., a floating gate transistor, having a gate electrode connected to a word line, a source electrode connected to a signal ground, and a drain electrode connected to a bit line. To read data from a selected memory cell, the bit line to which the selected memory cell is connected to a sense amplifier and a word line to which the selected memory cell is connected is driven by a word line voltage.
Traditional signal-bit ROM memory cells include a transistor having a threshold voltage that is set at one of two levels so that the memory cell stores one bit of data. To store more data, "multi-level" (or "multi-bit") devices have been proposed that utilize more than two threshold voltage levels to allow a signal memory cell to store multiple bits of data.
Various types of multi-level memories are possible. In one type, the gate length or gate width of the transistor of each memory cell is varied so that the current flowing when the memory cell is accessed may be set at various values. In other types of multilevel memories, the quantity of impurity ions injected into the metal oxide semiconductor (MOS) transistor of each memory cell is varied so that the threshold voltage of the MOS transistor may be set at various values.
FIG. 1 illustrates relationships between predetermined word line voltage thresholds WL0-WL1 and threshold voltage distributions Vth1-Vth4 for a multi-bit ROM. Each memory cell of multi-bit ROM may be classified as having one of four logic states 00-11, based on the relationship of its threshold voltage to the word line voltage level thresholds WL0-WL1.
FIG. 2 is a diagram showing reference voltages applied to a word line in a memory device such as the memory device 1 illustrated in FIG. 3 during a data reading operation for a multi-bit memory cell. While the word line is driven at a first word line voltage WL0, a sense amplifier circuit 17 detects whether a current (cell current) flows through the selected memory cell. Next, a second word line voltage WL1 higher than the first word line voltage WL0 is applied to the word line while the sense amplifier 17 determines whether a cell current flows through the selected memory cell. A third word line voltage WL2 higher than the first and second word line voltages WL0, WL1 is then applied to the word line while the sense amplifier determines whether a cell current flows through the memory device. As is known to those skilled in the art, the word line voltage at which the memory cell begins to exhibit current flow indicates the logic state of the memory cell. Generally, it is very important that the word line voltages WL0-WL2 are precisely controlled to prevent data sensing errors.
A typical multi-level memory device 1, illustrated in FIG. 3, includes an array 10 of multi-bit memory cells connected to word lines and bit lines (not shown). The word lines are selected by a pre row decoder circuit 11 and a block decoder circuit 12 in response to an address Ai applied thereto. A word line voltage generating circuit 13 generates a word line voltage VP and applies it to a selected word line via the pre-row decoding circuit 11 and the block decoder circuit 12. The voltage VP has different voltage levels, for example, the word line voltages WL0, WL1, WL2 illustrated in FIG. 2. The word line voltage generating circuit 13 receives a power supply voltage VCC/VPP from a voltage source 14, and generates the word line voltage VP therefrom. A bit line of the array 10 is selected by a column decoder circuit 15 and a column pass gating circuit 16, and a sense amplifier circuit 17 connected to the selected bit line detects whether a cell current flows in a memory cell connected to the selected bit line.
A conventional word line voltage generating circuit 13 for use in the memory device 1 of FIG. 3 and described in U.S. Pat. No. 5,457,650 is depicted in FIG. 4. The word line voltage generating circuit 13 has three dummy cells MO01, M10, M11, each comprising an NMOS transistor. The sources of the dummy cells M01, M10, M11 are grounded and their drains and gates are connected to a PMOS transistor 47 through resistors RM11, RM22, RM33. The gate of the transistor 47 receives a signal CEB, while the source of the transistor 47 receives a power supply voltage VCC/VPP. The drains of the dummy cells M01, M10, M11 are connected to the gates of NMOS transistors 41, 42 and 43, respectively. The sources of the transistors 41, 42 and 43 are grounded through a resistor RM44, and the drains of the transistors 41, 42 and 43 are connected to the drains of PMOS transistors 44, 45, 46, respectively. The gates of the transistors 44, 45, 46 receive signals NO.sub.-- ACT1, NO.sub.-- ACT2, NO.sub.-- ACT3, and their sources receive the power supply voltage VCC/VPP. An output voltage VP is produced at an output node connected to the sources of the transistors 41, 42, 43 and the resistor RM44.
The resistors RM11, RM22, RM33 typically have high resistances. The transistors 41, 42, 43 are typically enhancement-mode devices having threshold voltages that are nearly equal to 0V. When the signal CEB supplied to the gate of the PMOS transistor 47 is at a low level, the voltage at a node 4B is limited at approximately the threshold voltage of the dummy cell transistor M01, as the dummy transistor conducts when the voltage at node 4B rises above a threshold voltage of the dummy cell transistor M01. Similarly, the voltage at a node 4C is limited at approximately the threshold voltage of the dummy cell transistor M10 and the voltage at a node 4D is limited at approximately the threshold voltage of the dummy cell transistor M11.
Enhancement mode transistors 41, 42, 43 typically have threshold voltages nearly equal to 0V. When a first select signal NO.sub.-- ACT1 applied to a first transistor 44 is asserted low, the output voltage VP is approximately the same as the threshold voltage of the dummy cell transistor M01 (i.e., the voltage at a node 4B). When a second select signal NO.sub.-- ACT2 is asserted low, the output voltage VP is approximately the same as the threshold voltage of the dummy cell transistor M10. When a third select signal NO.sub.-- ACT3 is asserted low, the output voltage VP is approximately the same as the threshold voltage of the dummy cell transistor M11. As the output voltage VP of the word line generating circuit 13 is applied by the pre row decoder circuit 11 to a selected word line of the cell array 10.
The above-described word line voltage generating circuit 13 can compensate for upward fluctuation of the output voltage VP due, for example, to fluctuations in the power supply voltage VCC/VPP or to variations in the characteristics of memory cells driven by the word line voltage generating circuit 13. However, the word line voltage generating circuit 13 typically cannot boost the output voltage VP above the selected threshold voltage, as the threshold voltages of the dummy cells M01, M10, M11 are typically fixed. In addition, the threshold voltages of the transistors 41, 42, 43 may vary, causing variation in the output voltage VP. Moreover, if the source voltages of the transistors 41, 42, 43 are altered, their threshold voltages typically change due to a "body effect" well known to those skilled in the art. Since the source voltages of the transistors 41, 42, 43 are different for each sensing voltage level applied, the amount of the threshold voltage variation of each transistor 41, 42, 43 also typically differs. This may reduce the sensing margin for the sense amplifier circuit, and thus may reduce data sensing reliability of the memory device.